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micro pmu with 0.8 a buck , two 300 ma ldos supervisory, w atchdog and manual reset data sheet ADP5042 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks a nd registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2010 - 2011 analog devices, inc. all rights reserved. features input voltage range: 2. 3 v to 5.5 v one 0.8 a b uck r egulator two 3 0 0 ma ldo s 20- l ead, 4 mm 4 mm lfcsp package initial r egulator a ccuracy : 1 % over c urrent and t hermal protection soft s tart under voltage l ockout open d rain p rocessor r eset with thr eshold monitoring 1.5% threshold accuracy over the full temperate range guaranteed reset output valid to v cc = 1 v du al w atchdog for secure systems watchdog 1 controls reset watchdog 2 controls reset and regulators power cycle buck k ey s pecifications cu rrent m ode topology for excellent transient response 3 mhz operating frequency use s tiny multi layer inductors and capacitors mode pin selects f orced pwm or a uto pfm/psm modes 100% d uty c ycle low dropout mode ldo s k ey s pecifications low v in from 1.7 v to 5. 5 v stable with1 f ceramic output capacitors high psrr , 60 db psrr up to 1 k hz / 10 khz low output noise 110 v rms typical output noise at v out = 2.8 v low dropout voltage: 1 5 0 mv at 30 0 ma load ? 40 c to + 125 c junction temperature range high level block dia gram f pw m psm / pw m mo d e sw vo u t 1 pg n d c 6 10 f v o u t 1 a t 800 m a l 1 1 h en _ b k buc k en _ l d o 1 l d o 1 (d igi t a l ) en _ l d o 2 l d o 2 (ana l og ) supervisor microprocessor vi n 1 en 3 a vi n a vi n en 1 vi n 2 vi n 3 en 2 a g n d c 2 1 f vo u t 2 vo u t 3 w s t a t w d i 1 w d i 2 nr st o v o u t 2 a t 300 m a c 4 1 f v o u t 3 a t 300 m a c 5 4 . 7 f o n o f f o n o f f o n o f f vi n 1 = 2 . 3 v to 5 . 5 v a vi n r filt = 30? vi n 2 = 1 . 7 v t o 5 . 5 v mr c 1 1 f vi n 3 = 1 . 7 v t o 5 . 5 v c 3 1 f 088 1 1-001 figure 1 . general description the adp504 2 combine s one high performance buck regulator and two low dropout regulator s (ldo) in a small 20 - l ead lf csp to meet d emanding performance and board space requirements. the high switching frequency of the buck regulator enables use of tiny multilayer external components and minimizes the board space . the mode pin select s the buck mode of operation . w hen set to logic hig h, the buck regulators operate in forced pwm mode. when the mode pin is set to logic low , the buck regulators operate in pwm mode when the l oad is around the nominal value. w hen the load current falls below a predefined threshold the regulator operates in p ower s ave m ode (psm) improving the light - load efficiency. the low quiescent current, low dropout voltage , and wide i nput voltage range of the adp504 2 ldo s extend the battery life of portable devices. the two ldo s maintain power supply rejection greater t han 6 0 d b for frequencies as high as 10 k hz while operating with a low headroom voltage. each r egulator is activated by a high level on the respective en able pin . the ADP5042 is available with factory program mable default output voltage s an d can be set to a wide range of opti ons. the adp504 2 contains supervisory circuits that monitor power supply voltage levels and code execution integrity in microprocessor - based systems. they also provide power - on reset signals. a n on - chip dual watchdog timer can reset t he microprocessor or power cycle the system (w atchdog 2) if it fails to strobe within a preset timeout period.
ADP5042 data sheet rev. a | page 2 of 32 table of contents features .............................................................................................. 1 ? high level block diagram .............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? general specification ................................................................... 3 ? supervisory specification ............................................................ 3 ? buck specifications ....................................................................... 5 ? ldo1, ldo2 specifications ....................................................... 5 ? input and output capacitor, recommended specifications .. 6 ? absolute maximum ratings ............................................................ 7 ? thermal data ................................................................................ 7 ? thermal resistance ...................................................................... 7 ? esd caution .................................................................................. 7 ? pin configuration and function descriptions ............................. 8 ? theory of operation ...................................................................... 18 ? power management unit ........................................................... 18 ? buck section ................................................................................ 19 ? ldo section ............................................................................... 20 ? supervisory section ................................................................... 20 ? applications information .............................................................. 23 ? buck external component selection ....................................... 23 ? ldo capacitor selection .......................................................... 24 ? supervisory section ................................................................... 25 ? pcb layout guidelines .............................................................. 26 ? evaluation board schematics and artwork ............................ 27 ? suggested layout ........................................................................ 27 ? bill of materials ........................................................................... 28 ? application diagram ................................................................. 28 ? factory programmable options ................................................... 29 ? outline dimensions ....................................................................... 30 ? ordering guide .......................................................................... 30 ? revision history 10/11rev. 0 to rev. a updated outline dimensions ....................................................... 30 changes to ordering guide .......................................................... 30 12/10revision 0: initial version
data sheet ADP5042 rev. a | page 3 of 32 specific ations general specificatio n a vin , v in1 = (v out 1 + 0.5 v) or 2. 3 v, whichever is greater, avin, vin1 vin2, vin3, t a = 25c , unless otherwise noted . r egulators are enabled . table 1. parameter symbol description min typ max unit avin undervoltage lockout uvlo avin t j = ?40c to +125c input voltage rising uvlo avinrise 2.25 v input voltage falling uvlo avin fall 1.95 v shutdown current i gnd - sd enx = gnd 0.1 a enx = gnd, t j = ?40c to +125c 2 a thermal shutdown threshold ts sd t j rising 150 c thermal shutdown hysteresis ts sd - hys 20 c enx, wdix, mode, wmod , mr inputs input logic high v ih 2.5 v avin 5.5 v 1.2 v input logic low v il 2.5 v avin 5.5 v 0.4 v input leakage current (wmod e xcluded) v i- leakage enx = a vin or gnd 0.05 a enx = a vin or gnd, t j = ?40c to +125 c 1 a wmod input leakage current v i- lkg - wmod vwmod = 3.6 v, t j = ?40c to +125c 50 a open - drain outputs nrsto, wstat output voltage v ol a vin = 2.3 v to 5.5 v , i nrsto/wstat = 3 ma 30 mv open - drain reset output leakage current 1 a supervisory specific ation avin, vin1 = full operating range, t j = ? 40c to +125 c , unless otherwise noted. table 2. parameter min typ max unit test conditions/comments supply supply current (supervisory c ircuit o nly) 45 55 a a vi n = 5.5 v , en1 = en2 = en3 = vin 43 52 a a vi n = 3.6 v , en1 = en2 = en3 = vin reset threshold accuracy vth ? 0.8 % vth vth + 0.8 % v t a = 25c , sensed on voutx vth ? 1.5% vth vth + 1.5% v t j = ?40c to + 12 5c , s ensed on v out x reset threshold to output delay glitch im m unity (t uod ) 50 125 400 s v th = v uot ? 50 mv reset timeout period watchdog1 (t rp1 ) opt ion a 24 30 36 ms opt ion b 160 200 240 ms reset timeout period watchdog2 (t rp2 ) 3.5 5 7 ms v cc to reset delay (t rd ) 150 s vin1 falling at 1 mv/s regulators sequencing delay (t d1 , t d2 ) 2 ms watchdog inputs watchdog 1 timeout period (t wd1 ) opt ion a 81.6 102 122.4 ms opt ion b 1.28 1.6 1.92 sec
ADP5042 data sheet rev. a | page 4 of 32 parameter min typ max unit test conditions/comments watchdog 2 timeout period (t wd2 ) opt ion a 6 7.5 9 se c opt ion b w atchdog 2 d isabled opt ion c 3.2 4 4.8 min opt ion d 6.4 8 9.6 min opt ion e 11.2 16 19.2 min opt ion f 25.6 32 38.4 min opt ion g 51.2 64 76.8 min opt ion h 102.4 128 153.8 min watchdog 2 power off period (t poff ) opt ion a 21 0 ms opt ion b 400 ms wdi1 pulse width 80 ns v il = 0.4 v, v ih = 1.2 v wdi 2 pulse width 8 s v il = 0.4 v, v ih = 1.2 v watchdog status timeout period (t wdclear ) 11.2 sec wdi1 input current (source) 8 15 20 a v wdi1 = v cc , time average wdi1 input current (sink) ? 30 ?25 ? 14 a v wdi1 = 0, time average wdi2 internal pull - down 45 k manual reset input mr input pulse width 1 s mr glitch rejection 220 ns mr pull - up resistance 25 52 80 k mr to reset delay 280 ns v cc = 5 v
data sheet ADP5042 rev. a | page 5 of 32 b uck specifications av in, vin1 = 3.6 v, v out 1 = 1.8 v , t j = ?40c to +125c for minimum/maximum specifications, l = 1 h, c out = 10 f, and t a = 25c for typical specifications, unless otherwise noted. 1 t able 3. parameter test conditions/comments min typ max unit input characteristics input voltage range (vin1) 2.3 5.5 v output characteristics output voltage accuracy pwm mode, t a = 25 c , i load = 100 ma ?1 +1 % pw m mode ?2 +2 % vin 1 = 2. 3 v to 5.5 v, pwm mode , i load = 1 to 8 00 ma ?3 +3 % pwm to power save mode current threshold 100 ma input current characteristics dc operating current i load = 0 ma, device not switching 21 35 a shutdown current en x = 0 v, t a = t j = ?40c to +12 5c 0.2 1.0 a sw characteristics sw on resistance pfet 180 240 m pfet, avin = vin1 = 5 v 140 190 m nfet 170 235 m nfet , avin = vin1 = 5 v 150 210 m current limit pfet switch peak current limit 1100 1360 1600 ma active pull - down en1 = 0 v 75 oscillator frequency 2.5 3.0 3.5 mhz start - up time 250 s 1 all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc). ldo 1, ldo2 specifications avin = 3.6 v, v in2, v in3 = (v out 3 + 0.2 v) or 2.3 v , whichever is greater ; avin, vin1 vin2, vin3; i out = 10 ma; c in = c out = 1 f; t a = 25c, unless otherwise noted. table 4. parameter symbol conditions min typ max unit input voltage range v in2 , v in 3 t j = ?40c to +125c 1.7 5.5 v operating supply current (per ldo) i gnd i out = 0 a , v out = 3.3 v 15 a i out = 0 a, v out = 3.3 v, t j = ? 40c to +125c 50 a i out = 10 ma 67 a i out = 10 ma, t j = ?40c to +125c 105 a i out = 20 0 ma 100 a i out = 20 0 ma, t j = ?40c to +125c 245 a fixed output voltage accuracy v out 2 , v out 3 i out = 10 ma ?1 +1 % 100 a < i out < 30 0 ma ?2 +2 % v in2 , v in 3 = (v out2 , v out 3 + 0.5 v) to 5.5 v 100 a < i out < 30 0 ma ?3 +3 % v in2 , v in 3 = (v out2 , v out 3 + 0.5 v) to 5.5 v t j = ?40c to +125c regulation li ne regulation ?v out2 /?v in2 ?v out 3 /?v in3 v in2 , v in 3 = (v out 2 , v out 3 + 0.5 v) to 5.5 v ?0.03 +0.03 %/ v i out3 = 1 ma t j = ?40c to +125c
ADP5042 data sheet rev. a | page 6 of 32 parameter symbol conditions min typ max unit load regulation 1 ?v out2 /?i out2 ?v out 3 /?i out 3 i out 2 , v out 3 = 1 ma to 20 0 ma 0.002 %/ma i out 2 , v out 3 = 1 ma to 20 0 ma 0.0075 %/ma t j = ?40c to +125c dropout voltage 2 v dropout v out 2 , v out 3 = 3.3 v i out2 , i out3 = 10 ma 4 mv i out2 , i out3 = 10 ma, t j = ?40c to +125c 5 mv i out2 , i out3 = 2 0 0 ma 60 mv i out2 , i out3 = 20 0 ma, t j = ?40c to +125c 100 mv active pull - down r pdldo en2/ en 3 = 0 v 600 start - up time t start - up v out 2 , v out 3 = 3.3 v 85 s current - limit threshold 3 i limit t j = ?40c to +125c 335 470 ma output noise out ldo2noise 10 hz to 100 khz, v in3 = 5 v, v out 3 = 3.3 v 123 v rms 10 hz to 100 khz, v in3 = 5 v, v out 3 = 2.8 v 110 v rms 10 hz to 100 khz, v in3 = 5 v, v out 3 = 1.5 v 59 v rms out ldo1noise 10 hz to 100 khz, v in2 = 5 v, v out 2 = 3.3 v 140 v rms 10 hz to 100 khz, v in2 = 5 v, v out 2 = 2 .8 v 129 v rms 10 hz to 100 khz, v in2 = 5 v, v out 2 = 1.5 v 66 v rms power supply rejection ratio psrr 1 khz, v in2 , v in3 = 3.3 v, v out2, out 3 = 2.8 v, i out = 100 ma 66 db 100 khz, v in2 , v in 3 = 3 .3 v, v out2 , v out 3 = 2.8 v , i out = 100 ma 57 db 1 mhz, v in2 , v in3 = 3.3 v, v out2 , v out 3 = 2.8 v, i out = 100 ma 60 db 1 based on an end - point calculation using 1 ma and 10 0 ma loads. 2 dropout voltage is defined as the input - to - output voltage differential when the input voltage is set to the nominal output voltage. this applies only for output voltages above 2.3 v. 3 current - limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. for example, the current limit for a 3 . 0 v output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 v, or 2.7 v. input and output cap acitor, recommended specifications table 5. parameter symbol conditions min typ max unit minimum output capacitance (b uck ) 1 c min1 t j = ?40c to +125c 7 40 f minimum input and output capacitance 2 (ldo1 , ldo2 ) c min23 t j = ?40c to +125c 0.70 f capacitor esr r esr t j = ?40c to +125c 0.001 1 1 the minimum output capa citance should be greater than 4 . 7 f over the full range of operating conditions. the full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. 2 the minimum input and output capacitance should be greater than 0. 70 f over the full range of operating conditions. the full range of operating conditions in the application must be considered during device selection to ensure tha t the minimum capacitance specification is met. x7r and x5r type capacitors are recommended, y5v and z5u capacitors are not recommended for use with ldos or the buck.
data sheet ADP5042 rev. a | page 7 of 32 absolute maximum rat ings table 6. parameter rating avin, vinx , voutx, en x , mode , mr , wdi x , wmod, wstat, nrsto to gnd ? 0.3 v to + 6 v storage temperature range ? 65c to +150c operating junction temperature range ? 40c to +125c soldering conditions jedec j - std -020 esd human body model 3000 v esd charged device model 1500 v esd machine model 100 v stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other cond itions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal data absolute maximum ratings apply individually only, not in combination. the adp504 2 can be damaged when the junction temperature limits are exceeded. monitoring ambient temperature does not guarantee that the junction temperature is within the specified temperature limits. in applications with high power dissipation and poor thermal resistance , the maximum ambient temperature may have to be derated. in applications with moderate power dissipation and low pcb thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the jun ction temperature is within specification lim its. the junction temperature of the device is depende nt on the ambient temperature , the power dissipation of the device (p d ) , and the junction - to - ambient ther mal resistance of the package . maximum junction tem perature is calculated from the ambient temperature and power dissipation using the formula t j = t a + (p d ja ) junction - to - ambient thermal resistance ( ja ) of the package is based on modeling and calculation using a 4 - layer board. the junction - to - ambient thermal resistance is highly dependent on the application and board layout. in applications where high max imum power dissipation exists, close attention to thermal board design is required. the value of ja may vary, depending on pcb material, layout, and environmental conditions. the specified value of ja is based on a four - layer, 4 3 , 2.5 oz copper boar d, as per jedec standard . for additional information, see the an - 772 application note , a design and manuf acturing guide for the lead frame chip scale (lfcsp) . thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 7 . thermal resistance package type ja jc unit 20- lead , 0.5 mm p itch l fcsp 38 4.2 c/w esd caution
ADP5042 data sheet rev. a | page 8 of 32 pin configuration and fu nction descriptions ADP5042 top view (not to scale) notes 1. exposed pad should be connected to agnd. 2. nc = no connect. do not connect to this pin. 14 13 12 1 3 4 vout2 15 wstat vin2 wdi2 11 vout1 nc vin3 2 vout3 en3 5 nrsto 7 v i n 1 6 a v i n 8 s w 9 p g n d 1 0 e n 1 1 9 w d i 1 2 0 1 8 w m o d 1 7 m o d e 1 6 e n 2 mr 08811-002 figure 2. pin configurationview from top of the die table 8. preliminary pin function descriptions pin no. mnemonic description 1 nc do not connect to this pin. 2 vout3 ldo2 output voltage and sensing input. 3 vin3 ldo2 input supply (1.7 v to 5.5 v). 4 en3 enable ldo2. en3 = high: turn on ldo2; en3 = low: turn off ldo2. 5 nrsto open-drain reset output, active low. 6 avin regulators housekeeping and supe rvisory input supply (2.3 v to 5.5 v). 7 vin1 buck input supply (2.3 v to 5.5 v). 8 sw buck switching node. 9 pgnd dedicated power ground for buck regulator. 10 en1 enable buck. en1 = high: turn on buck; en1 = low: turn off buck. 11 vout1 buck sensing node. 12 wdi2 watchdog 2 (long timeout) refresh input from processor. can be disabled only by factory option. 13 vin2 ldo1 input supply (1.7 v to 5.5 v). 14 vout2 ldo1 output voltage and sensing input. 15 wstat open-drain watchdog timeout status. wstat = high: watchdog 1 timeout or power-on reset; wstat = low: watchdog 2 timeout. auto cleared after one second. 16 en2 enable ldo1. en2 = high: turn on ldo1. en2 = low: turn off ldo1. 17 mode buck mode. mode = high: buck regulator operates in fixed pwm mode; mode = low: buck regulator operates in pulse skipping mode (psm) at light lo ad and in constant pwm at higher load. 18 wmod watchdog mode. wmod = low: watchdog 1 normal mode ; wmod = high: watchdog 1 cannot be disabled by a three-state condition applied on wdi1. 19 wdi1 watchdog 1 refresh input from processor. if wdi1 is in high-z and wmod is low, watchdog 1 is disabled. 20 mr manual reset input, active low. tp agnd analog ground (tp = thermal pad). exposed pad should be connected to agnd.
data sheet ADP5042 rev. a | page 9 of 32 typical performance characteristics vin1 = vin2 = vin3 = avi n = 5.0 v, t a = 25c, unless otherwise noted. 08811-003 ch1 2.0v/div 1m? b w 20.0m ch2 2.0v/div 1m? b w 500m ch3 2.0v/div 1m? b w 20.0m a ch1 1.76v 200s/div 50.0ms/s 20.0ns/pt 1 2 3 vout1 vout2 vout3 figure 3 . 3 - channel start - up waveforms 0 0.1 0.2 0.3 0.4 0.5 0.6 1.0 0.9 0.8 0.7 2.3 2.8 3.3 3.8 4.3 4.8 5.3 system quiescent current (ma) input vo lt age (v) 088 1 1-004 vout1 = 1.8v, vout2 = vout = 3.3v figure 4 . system quiescent curr ent ( su m of all the input c urrents) vs. input volt age, vout1 = 1.8 v, vout2 = vout3 = 3.3 v 08811-005 ch1 2.0v/div 1m? b w 20.0m ch2 2.0v/div 1m? b w 500m ch3 100ma/div 1m? b w 20.0m ch4 5.0v/div 1m? b w 500m a ch1 2.92v 50s/div 50.0ms/s 20.0ns/pt 2 4 1 3 sw vout1 en iin figure 5 . buck startup, vout1 = 1.8 v, i out1 = 2 0 ma 08811-006 ch1 4.0v/div 1m? b w 20.0m ch2 3.0v/div 1m? b w 500m ch3 200ma/div 1m? b w 20.0m ch4 5.0v/div 1m? b w 500m a ch1 2.24v 50s/div 20.0ms/s 50.0ns/pt 4 2 1 3 sw vout1 load en figure 6 . buc k startup, vout 1 = 1.8 v, i out2 = 20 ma 3.22 3.24 3.26 3.28 3.30 3.32 3.34 output vo lt age (v) output current (a) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 088 1 1-007 +25 c ?40 c +85 c fig ure 7 . buck load regulation across temperature, vout1 = 3.3 v, auto mode 1.775 1.780 1.785 1.790 1.795 1.800 1.805 1.810 1.815 1.820 1.825 1.830 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 output current (a) output voltage (v) +25 c ?40 c +85 c 088 1 1-008 figure 8 . buck load regulation across temperature, vout 1 = 1.8 v, auto mode
ADP5042 data sheet rev. a | page 10 of 32 1.784 1.785 1.786 1.787 1.788 1.789 1.790 1.791 1.792 1.793 1.794 1.795 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 ?40 c +25 c +85 c output current (a) output voltage (v) 088 1 1-009 figure 9 . buck load regu lation across temperature , vout1 = 1.8 v, pwm mode 1.790 1.791 1.792 1.793 1.794 1.795 1.796 1.797 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 output current (a) output voltage (v) vin = 5.5v vin = 4.5v vin = 3.6v 088 1 1-010 figure 10 . buck load regula tion across input voltage, vout1 = 1.8 v, pwm mode 0 10 20 30 40 50 60 70 80 90 100 0.0001 0.001 0.01 0.1 1 efficienc y (%) output current (a) 3.6v 4.5v 5.5v 088 1 1-0 1 1 figure 11 . buck efficiency vs. load current, across input voltage, vo ut1 = 3.3 v, auto mode 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 efficienc y (%) output current (a) 3.6v 4.5v 5.5v 088 1 1-012 figure 12 . buc k efficiency vs. load current, across input voltage, vout1 = 3.3 v, pwm mode 0 10 20 30 40 50 60 70 80 90 100 0.0001 0.001 0.01 0.1 1 efficienc y (%) output current (a) 2.4v 3.6v 4.5v 5.5v 088 1 1-013 figure 13 . buc k efficiency vs. load current, across input voltage, vout 1 = 1.8 v, au to mode 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 efficienc y (%) i out (a) 2.4v 3.6v 4.5v 5.5v 088 1 1-014 figure 14 . buck efficiency vs. load current, across input voltage, vout2 = 1.8 v, pwm mode
data sheet ADP5042 rev. a | page 11 of 32 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 efficienc y (%) output current (a) +25oc ?40oc +85oc 088 1 1-015 figure 15 . buck efficiency vs. load current, across temperature, vout1 = 1.8 v, pwm mode 0 10 20 30 40 50 60 70 80 90 100 0.0001 0.001 0.01 0.1 1 efficienc y (%) output current (a) +25 c ?40 c +85 c 088 1 1-016 figure 16 . buck efficiency vs. load current, across temperature, vout1 = 3.3 v, auto mode 0 10 20 30 40 50 60 70 80 90 100 0.0001 0.001 0.01 0.1 1 efficienc y (%) output current (a) +25 c ?40 c +85 c 088 1 1-017 figure 17 . buck efficiency vs. load current, across temperature, vout 1 = 1.8 v, auto mode 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 2.6 3.6 4.6 5.6 input voltage (v) output current (a) 088 1 1-018 figure 18 . buck dc current capability vs. input voltage, vout 1 = 1.8 v 2.85 2.90 2.95 3.00 3.05 3.10 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 frequenc y (mhz) +25 c ?40 c +85 c 088 1 1-019 output current (a) figure 19 . buck switching frequency vs. output current, across temperature, vout 1 = 1.8 v, pwm mode 08811-020 ch1 20.0mv/div b w 20.0m ch2 200ma/div 1m? b w 20.0m ch3 2.0v/div 1m? b w 20.0m a ch1 2.4mv 5.0s/div 20.0ms/s 50.0ns/pt 1 2 3 vout i sw sw figure 20 . typical wavefor ms, vout1 = 3.3 v, i out1 = 30 ma, auto mode
ADP5042 data sheet rev. a | page 12 of 32 08811-021 ch1 2.0v/div 1m? b w 20.0m ch2 50.0mv/div b w 20.0m ch3 500ma/div b w 20.0m a ch1 1.56mv 5.0s/div 200ms/s 5.0ns/pt 2 3 1 vout i sw sw figure 21 . typical waveforms, vout 1 = 1.8 v, iout2 = 30 ma, auto mode 08811-022 ch1 2.0v/div 1m? b w 20.0m ch2 50.0mv/div b w 20.0m ch3 500ma/div b w 20.0m a ch1 1.56mv 500ns/div 200ms/s 5.0ns/pt 2 3 1 vout i sw sw figure 22 . typical waveforms, vout1 = 1.8 v, iout1 = 30 ma, pwm mode 08811-023 ch1 20.0mv/div b w 20.0m ch2 200ma/div 1m? b w 20.0m ch3 2.0v/div 1m? b w 20.0m a ch1 2.4mv 200ns/div 500ms/s 2.0ns/pt 1 2 3 vout i sw sw figure 23 . typical waveforms, vout 1 = 3.3 v, iout2 = 30 ma, pwm mode 08811-024 ch1 3v/div b w 20.0m ch2 50mv/div b w 20.0m ch3 900mv/div 1m? b w 20.0m a ch3 4.79v 100s/div 10.0ms/s 100ns/pt 1 3 vin vout sw 2 figure 2 4 . buck response to line transient, input voltage from 4.5 v to 5.0 v, vout1 = 3.3 v, pwm mode 08811-025 ch2 50mv/div b w 20.0m ch3 1v/div 1m ? b w 20.0m ch4 2v/div 1m ? b w 20.0m a ch3 4.96mv 100 s/div 20ms/s 100ns/pt 2 3 4 vin vout sw figure 25 . b uck response to line transient, v in = 4.5 v to 5.0 v, vout 1 = 1.8 v, pwm mode 08811-026 ch1 4v/div b w 20.0m ch2 50mv/div 1m ? b w 20.0m ch3 50ma/div 1m ? b w 20.0m a ch3 44ma 200 s/div 10ms/s 100ns/pt 2 3 1 sw vout iout figure 26 . buck response to load transient, iout1 from 1 ma to 50 ma, vout1 = 3.3 v, auto mode
data sheet ADP5042 rev. a | page 13 of 32 08811-027 ch1 4v/div b w 20.0m ch2 50mv/div b w 20.0m ch3 50ma/div 1m ? b w 20.0m a ch3 28ma 200 s/div 5ms/s 200ns/pt 2 3 1 vout sw v out load figure 27 . buck respon se to load transient, iout2 from 1 ma to 50 ma, vout2 = 1.8 v, auto mode a ch3 86ma 2 3 1 vout sw load 088 1 1-028 ch1 4v/div b w 20.0m ch2 50mv /div b w 20.0m ch3 50ma /div 1m ? b w 20.0m 200 s/div 10ms/s 100ns/pt figure 28 . buck response to load transient, i out1 from 20 ma to 14 0 ma, vout1 = 3.3 v, auto mode 3 4 2 088 1 1-029 vout1 load sw ch2 4v/div 1m ? b w 20.0m ch3 50mv/div 1m ? b w 20.0m ch4 50ma/div 1m ? b w 20.0m 200 s/div 50ms/s 20ns/pt a ch3 145ma figure 29 . buck response to load transient, i out2 from 20 ma to 180 ma, vout1 = 1.8 v, pwm mode 1 2 3 088 1 1-030 vout en iin a ch2 1.14v ch1 1v/div 1m ? b w 500m ch2 3v /div 1m ? b w 500m ch3 50ma /div 1m ? b w 20.0m 50 s/div 2ms/s 500ns/pt figure 30 . ldo1 startup, vout3=1.5 v, iout3 = 5 ma 088 1 1-031 1 2 3 vout iin en a ch2 1.14v ch1 1v/div 1m ? b w 500m ch2 3v /div 1m ? b w 500m ch3 50ma /div 1m ? b w 20.0m 100 s/div 1ms/s 1.0 s/pt figure 31 . ldo2 startup, vout3=3.3 v, iout3 = 5 ma 1.500 1.502 1.504 1.506 1.508 1.510 0.0001 0.001 0.01 0.1 output vo lt age (v) output current (a) 3.3v 4.5v 5.0v 5.5v 088 1 1-032 figure 32 . ldo1 load regulation across input voltage, vout2 = 1.5 v
ADP5042 data sheet rev. a | page 14 of 32 0.0001 0.001 0.01 0.1 output vo lt age (v) output current (a) 1.47 1.48 1.49 1.5 1.51 1.52 1.53 +85 c +25 c ?40 c 088 1 1-033 figure 33 . ldo1 load regulation across temperature, vin2 = 3.3 v, vout 2 = 1.5 v 1.480 1.485 1.490 1.495 1.500 1.505 1.510 1.515 1.520 3.6 4.5 5.0 5.5 output vo lt age (v) input vo lt age (v) 100 a 1ma 10ma 100ma 150ma 088 1 1-034 figure 34 . ldo1 line regulation across output load, vout2 = 1.5 v 3.25 3.26 3.27 3.28 3.29 3.30 3.31 3.32 3.33 3.34 3.35 0.0001 0.001 0.01 0.1 output vo lt age (v) output current (a) 3.6v 4.5v 5.0v 5.5v 088 1 1-035 figure 35 . ldo2 load regulation across input voltage, vout3 = 3.3 v 3.25 3.26 3.27 3.28 3.29 3.30 3.31 3.32 3.33 3.34 3.35 0.0001 0.001 0.01 0.1 output vo lt age (v) output current (a) +85 c +25 c ?40 c 088 1 1-036 figure 36 . ldo2 load regulation across temperature, vin3 = 3.6 v, vout3 = 3.3 v 3.280 3.285 3.290 3.295 3.300 3.305 3.310 3.315 3.320 3.325 3.6 4.5 5.0 5.5 output vo lt age (v) input vo lt age (v) 100 a 1ma 10ma 100ma 150ma 088 1 1-037 figure 37 . ldo2 line regulation across output load, vout3 = 3.3 v 0 0.05 0.10 0.15 load (a) current (a) 088 1 1-038 0 50 100 150 200 250 figure 38 . ldo 2 ground current vs. output load, vout3 = 2.8 v
data sheet ADP5042 rev. a | page 15 of 32 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 2.3 2.8 3.3 3.8 4.3 4.8 5.3 5.8 ground current (ma) input vo lt age (v) 1a 100 a 1ma 10ma 100ma 150ma 088 1 1-039 figure 39 . ldo 2 ground current vs. input voltage, across output load, vout3 = 2.8 v 3 1 088 1 1-040 vout iout ch1 50mv/div 1m ? b w 500m ch3 50ma/div 1m ? b w 20.0m 200 s/div 500ks/s 2.0 s/pt a ch3 28ma figure 40 . ldo2 response to load transient, iout3 from 1 ma to 80 ma, vout3 = 3.3 v 1 3 088 1 1-041 iout vout ch1 50mv/div 1m ? b w 500m ch3 50ma/div 1m ? b w 20.0m 200 s/div 500ks/s 2.0 s/pt a ch3 50ma figure 41 . ldo1 response to load transient, iout3 from 1 ma to 80 ma, vout2 = 1.5 v 08811-042 2 1 2 2 ch1 10.0mv/div ch2 800mv /div a ch2 5.33v 1m? b w 20.0m vout vin b w 20.0m figure 42 . ldo2 response to line transient, input voltage from 4.5 v to 5.5 v, vout3 = 3.3 v 08811-043 2 1 ch1 10.0mv/div ch2 800mv /div a ch2 5.33v b w 20.0m 1m? b w 20.0m vout vin 2 figure 43 . ldo1 line transient vin = 4.5 v to 5.5 v , vout2 = 1.5 v load current (a) output voltage (v) 0 0.1 0.2 0.3 0.5 0 1.0 1.5 2.0 2.5 3.0 0.4 0.5 0.6 0.7 0.8 5.5v 4.5v 3.6v 08811-056 figure 44 . ldo1, ldo2 output current capability vs. input voltage
ADP5042 data sheet rev. a | page 16 of 32 load (ma) rms noise ( v) 08811-044 100 10 ch 2 ; v out = 3. 3 v; vin = 5v ch 2 ; v out = 3. 3 v; vin = 3. 6 v ch 2; v out = 2. 8 v; vi n = 3. 1 v ch 2 ; v out = 1. 5 v; vin = 5v ch 2 ; v out = 1. 5 v; vin = 1. 8 v 0.0001 0.001 0.01 0.1 1 10 100 1k figure 45 . ldo1 output noise vs. load current, across input and output voltage load (ma) rms noise ( v) 08811-045 100 10 ch3; vout = 3.3v; vin = 5v ch3; vout = 3.3v; vin = 3.6v ch3; vout = 2.8v; vin = 3.1v ch3; vout = 1.5v; vin = 5v ch3; vout = 1.5v; vin = 1.8v 0.0001 0.001 0.01 0.1 1 10 100 1k figure 46 . ldo2 output noise vs. load current, across input and output voltage 10 100 1k 10k 100k 1m 10m frequency (hz) noise ( v/ hz) 08811-046 vo u t 2 = 3 . 3 v , v i n 2 = 3 . 6 v , i load = 3 0 0 m a vo u t 2 = 1 . 5 v , v i n 2 = 1 . 8 v , i load = 3 0 0 m a vo u t 2 = 2 . 8 v , v i n 2 = 3 . 1 v , i load = 3 0 0 m a 100 10 1.0 0.1 0.01 figure 47 . ldo1 noise spectrum across output voltage, vin = vout + 0.3 v vout3 = 3.3v, vin3 = 3.6v, i load = 300ma vout3 = 1.5v, vin3 = 1.8v, i load = 300ma vout3 = 2.8v, vin3 = 3.1v, i load = 300ma noise (v/hz) 100 10 1 0.1 0.01 1 10 100 1k frequency (hz) 10k 100k 1m 08811-055 figure 48 . ldo2 noise spectrum across output voltage, vin = vout + 0.3 v 100 10 1.0 0.1 0.01 10 100 1k 10k 100k 1m 10m frequency (hz) 08811-048 noise ( v/ hz ) vo u t 3 = 1 . 5 v , v i n 3 = 1 . 8 v , i load = 3 0 0 m a vo u t 2 = 2 . 8 v , v i n 2 = 3 . 1 v , i load = 3 0 0 m a vo u t 3 = 2 . 8 v , v i n 3 = 3 . 1 v , i load = 3 0 0 m a vo u t 2 = 3 . 3 v , v i n 2 = 3 . 6 v , i load = 3 0 0 m a vo u t 3 = 3 . 3 v , v i n 3 = 3 . 6 v , i load = 3 0 0 m a vo u t 2 = 1 . 5 v , v i n 2 = 1 . 8 v , i load = 3 0 0 m a figure 49 . ldo 1 vs. ldo2 noise spectrum ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m frequency (hz) psrr (db) 08811-049 1ma 10ma 100ma 200ma 300ma figure 50 . ldo2 psrr across output load, vin3 = 3.3 v, vout3 = 2.8 v
data sheet ADP5042 rev. a | page 17 of 32 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m frequency (hz) psrr (db) 08811-050 1ma 10ma 100ma 200ma 300ma figure 51 . ldo2 psrr across output load, vin3 = 3.1 v, vout3 = 2.8 v ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m frequency (hz) psrr (db) 08811-051 1ma 10ma 100ma 200ma figure 52 . ldo2 psr r across output load, vin3 = 5 v, vout3 = 3.3 v ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m frequency (hz) psrr (db) 08811-052 1ma 10ma 100ma 200ma 300ma figure 53 . ldo2 psrr across output load, vin3 = 3.6 v, vout3 = 3.3 v ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m frequency (hz) psrr (db) 08811-053 1ma 10ma 100ma 200ma 300ma figure 54 . ldo1 psrr across output load, vin2 = 5.0 v, vout2 = 1. 5 v ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m frequency (hz) psrr (db) 08811-054 1ma 10ma 100ma 200ma 300ma figure 55 . ldo1 psrr across output load, vin2 = 1.8 v, vout2 = 1.5 v
ADP5042 data sheet rev. a | page 18 of 32 theory of operation enab l e and mo d e c o n t r o l l d o 1 c o n t r o l so ft s t ar t pw m/ psm c o n t r o l buck 1 dr i ver an d an t i sh oo t t hr o u g h o sc i l l a t o r v r e f t h er ma l shu t d o w n sys t em und e r vol t a g e l o ck o u t r eset g en era t o r d eb o unc e pw m c o mp vd d a vd d a vd d a g m err o r a m p psm c o mp l o w curr en t i l i m i t r 1 r 2 ad p 504 2 vo u t 1 w mo d en w d 1 en w d 2 vi n 1 a vi n sw pg n d en 1 enb k en l d o 1 en l d o 2 mo d e mo d e en 2 en 3 sel o pmo d e_ f u ses vi n 2 a g n d vo u t 2 vi n 3 l d o 2 c o n t r o l r 3 r 4 en l d o 1 50 0 ? enb k 6 0 ? en l d o 2 50 0 ? d c b y a vd d a r 0 r 1 mr w d i 1 200 k? vdda 52k? 40 k ? w a t chd o g d et ect o r 1 w a t chd o g st a t u s mo n it o r w d i 2 w a t chd o g d et ect o r 2 po f f po f f vo u t 3 nr s t o w s t a t 088 1 1-057 figure 56 . functional block diagram power management uni t the adp504 2 is a micro power management uni t (micro pmu) combing one step - down (buck) dc - to - dc convertor , two low dropout linear regulator s (ldo s ) , and a supervisory circuit , with d ual watchdog, for processor control . the regulators are act ivated by a logic level high applied to the respective en p in . the en1 controls the b uck regulator, the en2 controls ldo1 , and the en3 controls ldo2. the ADP5042 has factory programmed output voltages and reset voltage threshold. other features available in this device are the mode pin to control the b uck switchin g operation, a status pin informing the external processor which watchdog caused a reset and push - button reset input. when a regulator is turned on, the output voltage is controlled th r ough a soft start circuit to avoid a large inrush current due to the di scharged output capacitors. the buck regulator can operate in forced pwm mode if the mode pin is at a logic high level. in forced pwm mode, the switching frequency of the buck is always constant and does not change with the load current. if the mode pin is at logic low level, the switching regulator operate s in auto pwm/psm mod e. in this mode, the regulator operate s at fixed pwm frequency w hen the load current is above the power saving current thresh old. when the load current falls below the power saving current threshold, the regulator enters power saving mode , where the switching occurs in bursts. the burst repetition is a function of the current load and the output capacitor value. this operating mode reduces the switching and quiescent current losses.
data sheet ADP5042 rev. a | page 19 of 32 thermal protection in the event that the junction temperature rises above 150c, the thermal shutdown circuit turns off the b uck and the ldo s. extreme junction temperatures can be the result of high current operation, poor circuit board design, or high ambient tempe rature. a 20c hysteresis is included so that when thermal shutdown occurs, the buck and ldo s do not return to operation until the on - chip temperature drops below 130c. when coming out of thermal shutdown, soft start is initiated. undervolta ge lockout to protect against battery discharge, undervoltage lockout (uvlo) circuitry is integrated in the system. if the input voltage on a vin drops below a typical 2.15 v uvlo threshold, all channels shut down. in the buck channel, both the power switch and the synchronous rectifier turn off. when the voltage on a vin rises above the uvlo threshold, the part is enabled once more. alternatively, the user can select device models with a uvlo set at a higher level, suitable for 5 v applications. for these mo dels, the device hits the turn - off threshold when the input supply drops to 3.65 v typical. enable/shutdown the adp504 2 ha s individual control pin s for each regulator. a logic level high applied to the enx pin activate s a regulator, a logic level low turns off a regulator. w hen regulators are turned off after a w atchdog 2 event (see the watchdog 2 input section ) , the reactivation of the regulator occurs with a factory programme d order ( see table 9 ) . the delay between the regulator activation ( t d1 , t d2 ) is 2 ms. table 9 . ADP5042 regulators sequencing regseq[1:0] regulators sequence (fi r st to last) 0 0 ldo1 ? ldo2 ? b uck 0 1 b uck ? ldo1 ? ldo2 1 0 ld o1 ? b uck ? ldo2 1 1 no s equence, all regulators start at same time buck section the buck use s a fixed frequency and high speed current mode architecture. the buck operate s with an input voltage of 2. 3 v to 5.5 v. control scheme the buck operate s with a fixed frequency, current mode pwm control architecture at medium to high loads for high efficiency but shift to a power save mode (psm) control scheme at light loads to lower the regulation power losses. when operating in fixed frequency pwm mode, the du ty cycle of the integrated switches is adjusted and regulates the output voltage. when operating in psm at light loads, the output voltage is controlled in a hysteretic manner, with higher output voltage ripple. dur ing part of this time, the converter is a ble to stop switching and enters an idle mode, which improves conversion efficiency. pwm mode in pwm mode, the buck operate s at a fixed frequency of 3 mh z , set by an internal oscillator. at the start of each oscillator cycle, the pfet switch is turned on, sending a positive voltage across the inductor. current in the inductor increases until the current sense signal crosses the peak inductor current threshold that turns off the pfet switch and turns on the nfet synchronous rectifier. this sends a negative v oltage across the inductor, causing the inductor current to decrease. the synchronous rectifier stays on for the rest of the cycle. the buck regulates the output voltage by adjusting the peak inductor current threshold. power save mode (psm) the buck smoot hly transition s to psm operation when the load current decreases below the psm current threshold. when the buck enter s power save mode, an offset is induced in the pwm regulation level, which makes the output voltage rise. when the output voltage reaches a level that is approximately 1.5% above the pwm regulation level, pwm operation is turned off. at this point, both power switches are off, and the buck enters an idle mode. the output capacitor discharges until the output voltage falls to the pwm regulatio n voltage, at which point the device drives the inductor to make the output voltage rise again to the upper threshold. this process is repeated while the load current is below the psm current threshold. psm current threshold the psm current threshold is se t to 100 ma. the buck employ s a scheme that enables this current to remain accurately con - trolled, independent of input and output voltage levels. this scheme also ensures that there is very little hysteresis between the psm current threshold for entry to and exit from the psm. the psm current threshold is optimized for excellent efficiency over all load currents. short - circuit protection the buck include s frequency foldback to prevent output current runaway on a hard short. when the voltage at the feedback pin falls below half the target output voltage, indicating the possi - bility of a hard short at the output, the switching frequency is reduced to half the internal oscillator frequency. the reduction in the switching frequency allows more time for the indu ctor to discharge, preventing a runaway of output current. soft start the buck ha s an internal soft start function that ramps the output voltage in a controlled manner upon startup, thereby limiting the inrush current. this prevents possible input voltage drops when a battery or a high impedance power source is connected to the input of the converter. current limit the buck has protection circuitry to limit the amount of positive current flowing through the pfet switch and the amount of negative current flo wing through the synchronous rectifier. the positive current limit on the power switch limits
ADP5042 data sheet rev. a | page 20 of 32 the amount of current that can flow from the input to the output. the negative current limit prevents the inductor current from reversing direction and flowing o ut of the load. 100% duty operation with a dropp in g input voltage or with an increase in load current, the buck may reach a limit where, even with the pfet switch on 100% of the time, the output voltage drops below the desired output voltage. at this limit , the buck transitions to a mode where the pfet switch stays on 100% of the time. when the input conditions change again and the required duty cycle falls, the buck immediately restarts pwm regulation without allowing overshoot on the output voltage. ldo section the adp5 04 2 contains two ldos with low quiescent current, low dropout linear regulator , and provides up to 300 ma of output current. drawing a low 1 5 a quiescent current (typical) at no load makes the ldo ideal for battery - operated portable equipm ent. the ldo operates with an input voltage range of 1.7 v to 5.5 v. the wide operating range makes these ldos suita ble for cascading configuration s where the ldo supply voltage is provided from the buck regulator. t he ldos also provide high power supply r ejection ratio (psrr) , low output noise, and excellent line and load transient response with just a small 1 f ceramic input and output capacitor. ldo2 is optimized to supply analog circuits because it offers better noise performance compared to ldo1. ldo 1 should be used in applications where noise performance is not critical. internally, one ldo consists of a reference, an error amplifier, a feedback voltage divider, and a pmos pass transistor. output current is delivered via the pmos pass device, which is con - trolled by the error amplifier. the error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. if the feedback voltage is lower than the reference voltage, the gate of the pmos device is pulled lower, allowing more current to flow and increasing the output voltage. if the feedback voltage is higher than the reference voltage, the gate of the pmos device is pulled higher, reducing the current flowing to the outp ut. supervisory section the ADP5042 provide s microprocessor supply voltage super - vision by controlling the reset input of the microprocessor . code execution errors are avoided during power - up, power - down, and brownout conditions by asserting a reset signal when the supply voltage is below a preset threshold and by allowing supply voltage stabilization with a fixed timeout reset pulse after the supply voltage rises above the threshold. in addition, problems with microprocessor code execution can be monit ored and corrected with a dual - watchdog timer . reset output the adp504 2 ha s an active - low, open - drain reset output. this output structure requires an external pull - up resistor to connect the reset output to a voltage rail that is no higher than 6 v. the resistor shoul d comply with the l ogic low and logic high voltage level requirements of the microprocessor while supplying input cur rent and leakage paths on the nrsto pin. a 10 k? resistor is ade quate in most situations. the reset output is asserted when the monitored rail is below the re set thresh old (v th ), when wdi 1 or wdi2 is not serviced within the watchdog timeout period (t wd 1 and t wd12 ) . reset remains asserte d for the duration of the reset active timeout period (t rp ) after v cc rises above the reset threshold or after the watchdog tim er times out. fi gure 57 illustrates the behavior of the reset output , nrsto, and it assumes that vout2 is selected as the rail to be monitore d and supplies the external pull - up conn ected to the nrsto output . r st o n r st o t r d t r d vout2 t r p 1 t r p 1 vout2 vout2 v t h v t h 0 v 1 v 0 v 1 v 0 v 088 1 1-058 fi gure 57 . reset timing diagram the reset threshold voltage and the sensed rail (vout1, vout2 , vout3 , or avin ) are factory programmed. refer to table 16 for a complete list of the reset thres holds available for the ADP5042. when monitoring the input supply voltage , a vin , if the selected reset threshold is below the uvlo level (factory programmable to 2.25 v or 3.6 v) the reset output , nrsto , is asserted low as s oon as the input voltage falls b elow the uvlo threshold. belo w the uvlo threshold , t he reset output is maintained low down to ~1 v vin. t his it to ensure that the reset output is not released whe n there is sufficient voltage on the rail supplying a processor to restart the processor oper ations. manual reset input t he adp504 2 feat ure s a manual reset input ( mr ) which , when driven low, asse rts the reset output. when mr transitions from low to high, reset remains asserted for the duration of the reset acti ve timeout period before deasserting. the mr input has a 52 k?, internal pull - up , connected to avin, so that the input is always high when unconnected. an external push - button switch can be connected between mr and groun d so that the user can generate a reset. debounce circuitry for this purpose is integrated on chip. noise immunity is provided on the mr input, and fast, negative - going transients of up to 100 ns (typical) are ignored. a 0.1 f capacitor between mr and ground provides additional noise immunity.
data sheet ADP5042 rev. a | page 21 of 32 watchdog 1 input the adp504 2 feature s a watchdog timer that monitors micro - processor activity. a timer circuit is cleared with every low - to - high or high - to - low logic t ransition on the watchdog input pin (wdi 1 ), which detects pulses as short as 8 0 ns. if the timer counts through the preset watchdog timeout period (t wd 1 ), reset is asserted. the microprocessor is required to toggle the wdi 1 pin to avoid being reset. failure of the mic roprocessor to toggle wdi 1 within the timeout period, therefore, indicates a code execution error, and the reset pulse generated restarts the microprocessor in a known state. as well as logic transitions on wdi 1 , the watchdog timer is also cleared by a re set assertion due to an undervoltage condition on the monitored rail . when reset is asserted, the watchdog timer is c leared and does not begin counting again until reset deassert s. watchdog 1 timer can be disabled by leaving wdi 1 floating or by three - stati ng the wdi1 driver. the pin wmod control s the w atchdog 1 operating mode . i f wmod is set to logic level low , w atchdog 1 is enabled as long as wdi1 is not in three - state . i f wmod is set to logic level high , w atchdog 1 is always active and cannot be disabled by a three - state condition. wmod input has an internal 200 k pull - down resistor. watchdog 1 timeout is factory set to two possible values as indicated in table 18. w d i 1 n r s t o t r p 1 t r p 1 t w d 1 v se n se d v t h 1 v 0 v 0 v 0 v 088 1 1-059 figure 58 . watchdog 1 t iming diagram watchdog 2 input the ADP5042 feature s an additional watchdog timer that monitors microprocessor activity in parallel to the first watchdog with a much longer timeout . t his provides additional security and safety in case w atchdog 1 is incorre ctly strobed . a timer circuit is cleared with every low - to - high or high - to - low logic t ransition on the watchdog input pin (wdi2), which detects pulses as short as 8 s. if the timer counts through the preset watchdog timeout period (t wd2 ), reset is asserte d , followed by a power cycle of all regulators . the microprocessor is required to toggle the wdi2 pin to avoid being reset and powered down. failure of the microprocessor to toggle wdi2 within the timeout period , therefore, indicates a code execution erro r, and the reset output nrsto is forced low for t rp2 . t hen , all the regulators are turn ed off for the t poff time . after the t poff period , t he regulators a re re - activated according to a predefined sequence ( see table 9 ). f inally , the reset line (nrsto) is asserted for t rp1 . this guarantee s a clean power - up of the system and proper reset. as well as logic transitions on wdi2, the watchdog timer is also cleared by a reset assertion due to an undervoltage condition on t he vth monito red rail which can be factory programmable betwe en vout1, vout2, vout 3 , and avi n ( see table 21) . when reset is asserted, the watchdog timer is cleared and does not begin counting again until reset deas serts. watchdog 2 timeout is factory set to seven possible values as indicated in table 19 . one additional option allows watchdog 2 to be factory disabled. a vi n / vi n x / en x v out1 v out2 v out3 n rsto w d i 2 w st a t 0 v 0 v 0 v 0 v 0 v t p o f f t r p 2 t w d 2 t r p 1 t r p 1 t w dcl e a r t d 1 t d 1 t d 2 v t h t d 2 088 1 1-060 figure 59 . watchdog 2 timing diagram (assuming that vout2 i s the monitored rail)
ADP5042 data sheet rev. a | page 22 of 32 watchdog status indicator in addition to the dual watchdog function, the ADP5042 features a watchdog status monitor available on the wstat pin. this pin can be queried by the external processor to dete rmine the origin of a reset. wstat is an open - drain output. wstat outputs a logic level depending on the condition that has generated a reset. wstat is forced low if the reset was generated because of a watchdog 2 timeout. wstat is pulled h igh, through ex ternal pull - up, for any other reset cause (watch dog 1 timeout, power failure or monitored voltage below threshold). the status monitor is automatically cleared (set to logic level high) 10 seconds after the nrsto low to high transition (t wdclea r ), processo r firmware must be designed being able to read the wstat flag before t wdclear expiration after a watchdog 2 reset. the wstat flag is not updated in the event of a reset due to a low voltage threshold detection or watchdog 1 event occurring within 10 second s after nrsto low to high transition. in this situation, wstat maintains the previous state (see state flow in figure 60). the external processor can further distinguish a reset caused by a watchdog 1 timeout from a power failure, status monitor wstat indicating a high level, by implementing a ram check or signature verification after reset. a ram check or signature failure indicates that a power failure ha s occurred , whereas a ram check or signature validation indi cates that a w atchdog 1 timeout ha s occurred. table 10 shows the possible watchdog decoded statuses. table 10 . watchdog status decoding wstat ram checksum reset origin high failed power fai lure high ok watchdog 1 low don't care watchdog 2 n o po w er a ppl i ed t o a vi n . a ll r eg u l a t o r s and su per vi so r y t urn ed o f f n o p o w e r po r st andb y w s t a t = h i g h w s t a t = h i g h r eset n o r ma l w st a t = l o w a vi n < vu vl o a ll en x = l o w a vi n > vu vl o t ran si t io n st a t e t ran si t io n st a t e t ran si t io n st a t e end o f po r w st a t t i meo u t (t w dcl e a r ) w st a t = 1 t ran si t io n st a t e a ll r eg u l a t o r s an d su per vi so r ac t i va t ed w d og 2 t i meo u t (t w d 2 ) w st a t = 0 end o f (t p o f f ) pu l se w d og 1 t i meo u t (t w d 1 ) an d w st a t t i meo u t w st a t = 1 w d og 1 t i meo u t (t w d 1 ) a ll en x = h ig h a c t i v e po w er o f f r ese t sh o r t a vi n < vu vl o end o f r eset pu l se (t r p 2 ) i n t erna l c i rcu i t b i a sed r eg u l a t o r s an d su per vi so r y n o t ac t i va t ed a vi n < vu vl o a vi n < vu vl o vmo n < vt h end o f r eset pu l se (t r p 1 ) 088 1 1-061 figure 60 . adp504 2 state flow
data sheet ADP5042 rev. a | page 23 of 32 a pplications informat ion buck external component selection trade - offs between performance parameters such as efficiency and transient respons e can be made by varying the choice of external components in the applications circuit, as shown in figure 66 . inductor the high switching frequency of the adp504 2 buck allows for the selection of small chip induct ors. for best performance, use inductor values between 0.7 h and 3 h. suggested inductors are shown in table 11 . the peak - to - peak inductor current ripple is calculated using the following equation: lfv vvv i sw in out in out ripple ? = ) ( where: f sw is the switching frequency. l is the inductor value. the minimum dc current rating of the inductor must be greater than the inductor peak current. the inductor peak current is calculated using the following equation: 2 )( ripple max load peak i ii + = inductor conduction losses are caused by the flow of current through the inductor, which has an associated internal dc resistance (dcr). larger sized inductors have smaller dcr, which may decrease inductor conduction losses. inductor core losse s are related to the magnetic permeability of the core mate rial. because the buck is high switching frequency dc - to - dc conv erters, shielded ferrite core material is recommended for its low core losses and low emi. table 11 . suggested 1.0 h inductors vendor model dimensions (mm) i sat (ma) dcr (m) murata lqm2mpn1r0ng0b 2.0 1.6 0.9 1400 85 murata lqm18fn1r0m00b 1.6 0.8 0.8 150 26 taiyo yuden cbmf1608t1r0m 1.6 0.8 0.8 290 90 coilcraft epl2014 - 102ml 2.0 2.0 1.4 900 59 tdk glfr1608t1r0m - lr 1.6 0.8 0.8 230 80 coilcraft 0603ls - 102 1.8 1.69 1.1 400 81 toko mdt2520 - cn 2.5 2.0 1.2 1350 85 output capacitor higher output capacitor values reduce the output voltage ripple and improve load transient response. whe n choosing this value, it is also important to account for the loss of capacitance due to output voltage dc bias. ceramic capacitors are manufactured with a variety of dielec - trics, each with a different behavior over temperature and applied voltage. capac itors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. x5r or x7r dielectrics with a voltage rating of 6.3 v or 10 v are recom - mended for best performance. y5v and z5u dielectri cs are not recommended for use with any dc - to - dc converter because of their poor temperature and dc bias characteristics. the worst - case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage is calcu - lated using the following equation: c eff = c out (1 ? tempco ) (1 ? tol ) where: c eff is the effective capacitance at the operating voltage. tempco is the worst - case capacitor temperature coefficient. tol is the worst - case component tolerance. in this example, the w orst - case temperature coefficient (temp co) over ?40c to +85c is assumed to be 15% for an x5r dielec tric. the tolerance of the capacitor (tol) is assumed to be 10% , and c out is 9.2481 f at 1.8 v, as shown in figure 61 . substituting these values in the equation yields c eff = 9.2481 f (1 ? 0.15) (1 ? 0.1) = 7.0747 f to guarantee the performance of the buck, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. 0 2 4 6 8 10 12 0 1 2 3 4 5 6 dc bias vo lt age (v) capacitance (f) 088 1 1-062 figure 61 . typical capacitor performance
ADP5042 data sheet rev. a | page 24 of 32 the peak - to - peak output voltage ripple for the selected output capacitor and inductor values is calculated using the following equation: ( ) out sw in ripple c l f v v = 2 2 out sw ripple c f i = 8 capacitors with lower equivalent series resistance (esr) are preferred to guarantee low output voltage ripple, as shown in the following equation: ripple ripple cout i v esr the effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 7 f and a maximum of 40 f. table 12 . suggested 10 f capacitors vendor type model case size voltage rating (v) murata x5r grm188r60j106 0603 6.3 taiyo yuden x5r jmk 107bj475 0603 6.3 tdk x5r c1608jb0j106k 0603 6.3 panasonic x5r ecj1vb0j106m 0603 6.3 the buck regulator require s 10 f output capacitors to guaran - t ee stability and response to rapid load variations and to transition in and out the pwm/psm modes. in ce rtain applications, wher e the buck regulator powers a processor, the operating state is known because it is controlled by software. in this condition, t he processor can drive the mode pin according to the ope rating state; consequently, it is possible to re duce the output capacitor from 10 f to 4.7 f because the regulator does not expect a large load var iation when working in psm mode ( see figure 62 ) . sw vi n 1 vi n 2 vi n 3 vo u t 1 vo u t 2 nr s t o pg n d vo u t 3 l 1 1 h c 6 4 . 7 f c 4 1 f r 1 10 0 k ? c 5 1 f c 2 4 . 7 f c 1 1 f c 3 1 f a vi n r fl t 30 ? v i n 2 . 3 v t o 5 . 5 v mi cr o pmu ad p 504 2 pr o c ess o r ana l o g sub -syst em vc o r e vdd i o r eset g pio 1 mo d e w d i g pio 2 en x g pio [x :y ] v a n a 3 088 1 1-063 figure 62 . processor system power ma nagement with psm/pwm control input capacitor higher value input capacitors help to reduce the input voltage ripple and improve transient response. maximum input capacitor current is calculated using the following equation: in out in out max load cin v v v v i i ) ( ) ( ? to m i n i mize supply noise, place the input capacitor as close to the vin pin of the buck as possible. as with the output capacitor, a low esr capacitor is recommended. the effective capacitance needed for stability, which includes temperature and dc bias effects , is a minimum of 3 f and a maximum of 10 f. a list of suggested capacitors is shown in table 13. table 13 . suggested 4.7 f capacitors vendor type model case size voltage rating (v) murata x5r grm188r60j475me19d 0603 6.3 taiyo yuden x5r jmk107bj475 0603 6.3 panasonic x5r ecj - 0eb0j475m 0402 6.3 ldo capacitor select ion output capacitor the adp504 2 ldo s are designed for operation with small, space - saving ceramic capacitors, but they function with most commonly used capacitors as long as care is taken with the esr value. the esr of the out put capacitor affects stability of the ldo control loop. a minimum of 0. 70 f capacitance with an esr of 1 ? or less is recom mended to ensure stability of the adp504 2 . transient response to changes in load current is also affected by output capacitance. using a larger value of output capacitance improves the transient response of the adp504 2 to large changes in load current. input bypass capacitor connecting a 1 f capacitor from vin2 and vin3 to gnd reduces the cir cuit sensitivity to printed circuit board (pcb) layout, especially when long input t races or high source impedance i s encountered. if greater than 1 f of output capacitance is required, increase the input capacitor to match it. table 14 . suggested 1.0 f capacitors vendor type model case size voltage rating (v) murata x5r grm155r61a105me15 0402 10.0 tdk x5r c1005jb0j105kt 0402 6.3 panasonic x5r ecj0eb0j105k 0402 6.3 taiyo yuden x5r lmk105bj105mv - f 0402 10.0
data sheet ADP5042 rev. a | page 25 of 32 input and output capaci tor properties use any good quality ceramic capacitors with the adp504 2 as long as they meet the minimum capacitance and maximum esr r equirements. ceramic capacitors are manufactured with a vari ety of dielectrics, each with a different behavior over temper ature and applied voltage. capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary tempe - rature range and dc bias conditions. x5r or x7r dielectrics with a voltage rating of 6.3 v or 10 v are recommended for best per formance. y5v and z5u dielectrics are not recommended for use with any ldo because of their poor temperature and dc bias characteristics. figure 63 depicts the capacitance vs. voltage bias characteristic of a 0402 1 f, 10 v, x5r capacitor. the voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating . in general, a capacitor in a larger package or higher voltag e rating exhibits better stability. the temperature variation of t he x5r dielectric is about 15% over the ?40c to +85c tempera - ture range and is not a function of package or voltage rating. 1 . 2 1 . 0 0 . 8 0 . 6 0 . 4 0 . 2 0 0 1 2 3 4 5 6 dc b i a s vo lta g e (v) capacitance (f) 088 1 1-064 figure 63 . capacitance vs. voltage characteristic use the following equation to determine the worst - ca se capa - citance accounting for capacitor variation over temperature, component tolerance, and voltage. c eff = c bias (1 ? tempco ) (1 ? tol ) where: c bias is the effective capacitance at the operating voltage. tempco is the worst - case capacitor temperatur e coefficient. tol is the worst - case component tolerance. in this example, the worst - case temperature coefficient (tempco) over ?40c to +85c is assumed to be 15% for an x5r dielectric. the tolerance of the capacitor (tol) is assumed to be 10% , and c bias is 0.94 f at 1.8 v as shown in figure 63. substituting these val ues into the following equation yields: c eff = 0.94 f (1 ? 0.15) (1 ? 0.1) = 0.719 f therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the ldo over temperature and tolerance at the chosen output voltage. to guarantee the pe rformance of the adp504 2 , it is imperative that the effects of dc bias, temperature, and toler ances on the behavior of the capacitors be evaluated for each application. supervisory section watchdog 1 input current to minimize watchdog input current (and minimize overall power consumption), leave wdi 1 low for the majority of the watchdog timeout period. when driven high, wdi 1 can draw a s much as 25 a. pulsing wdi 1 low - to - high - to - low at a low duty cycle reduces the effect of the large input current. when wdi 1 is unconnected and wmod is set to logic level low , a window comparator disconnects the watchdog timer from the reset output circui try so that reset is not asserted when the watchdog timer times out. negative - going v cc transients to avoi d unnecessary resets caused by fast power supply transien ts, t he adp504 2 is equipped with glitch rejection circuitry. the typic al performance characte ristic in fi gure 64 plots the monitored rail voltage, v th , t ransient duration vs. the transient magnitude. the curve show s combinations of transient magnitude and duration for which a reset is not generated for a 2 .93 v reset threshold part . for example, with the 2.93 v threshold, a transient that goes 100 mv below the threshold and lasts 8 s typically does not cause a reset, but if the transient is any larger in m agnitude or duration, a reset is generated. 100 0 90 0 80 0 70 0 60 0 50 0 40 0 30 0 20 0 10 0 0 0 . 1 1 1 0 10 0 c o mpara t o r o verdr i ve (% o f v t h ) transient duration (s) 088 1 1-065 fi gure 64 . maximum v th transient duration vs. reset threshold overdrive watchdog software considerations in implementing the watchdog strobe code of the micro - processor , quickly switching wdi 1 low to high and then high to low (minim izing wdi 1 high time) is desirable for current consumption reasons. however, a more effective way of using the watchdog function can be considered. a low - to - high - to - low wdi 1 pulse within a given subroutine prevents the watchdog from timing out. however, if the sub - routine becomes stuck in an infinite loop, the watchdog cannot detect this because the subroutine continues to toggle wdi 1 . a more effective coding scheme for detecting this error involves
ADP5042 data sheet rev. a | page 26 of 32 using a slightly longer watchdog timeout. in the program t hat calls the subroutine, wdi 1 is set high. the subroutine sets wdi 1 l ow when it is called. if the program executes without error, wdi 1 is toggled high and low with every loop of the program. if the subroutine enters an infinite loop, wdi 1 is kept low, the watchdog times out, and the microprocessor is reset (see figure 65). st ar t set wdi h ig h pr og ra m code subr outine set wdi low ret ur n infinite l oo p: wat chd og times o ut reset 088 1 1-066 figure 65 . watchdog flow diagram the second watchdog , refreshed through the wdi2 pin, is useful in applications wher e safety is a very critical factor and the system must recover from unwanted operations , f or exam ple, a processor stuck in a continuous loop where w atchdog 1 is kept refr eshed or environmental conditions that may unset or damage the processor port controll ing the wdi1 pin. in the event of a w atchdog 2 timeout , the ADP5042 power cycle s all the supplied rails to guarantee a clean processor start. adp 5042 mi cr oprocessor v cc vout1 vout2 nrsto wdi1 reset wdi2 vin1 i/ o i/ o v core vdd io 088 1 1-067 figure 66 . typical application s circuit pcb layout guideline s poor layout can affect ad p504 2 performance, causing electro - magnetic in terference (emi) and electromag netic compatibility (emc) problems, ground bounce, and voltage losses. poor layout can also affect regulation and stability. a good layout is implemented using the following guide lines: ? place the inductor, input capacitor, and output capacitor close to the ic using short tracks. these components carry high switching frequencies , and large tracks act as antennas. ? route the output voltage path away from the inductor and sw node to m inimize noise and magnetic interference. ? maximize the size of ground metal on the component side to help with thermal dissipation. ? use a ground plane with several vias connecting to the component side ground to further reduce noise interference on sensitiv e circuit nodes.
data sheet ADP5042 rev. a | page 27 of 32 evaluation board s chematics and artwor k sw vo u t 1 pg n d mo d e c 6 10 f l 1 1 h vi n 1 t p1 t p2 t p1 1 t p6 t p5 t p8 en 3 en 1 vi n 2 vi n 3 en 2 a g n d c 2 1 f vo u t 2 vo u t 3 w st a t w d i 1 w d i 2 n r st o t p1 2 c 4 1 f c 5 4 . 7 f vi n 1 = 2 . 3 v t o 5 . 5 v a vi n r f i l t 30 ? a vi n vi n 2 = 1 . 7 v t o 5 . 5 v c 1 1 f vi n 3 = 1 . 7 v t o 5 . 5 v c 3 1 f vo u t 1 a t 800m a vo u t 2 a t 300m a vo u t 3 a t 300m a t p4 t p9 t p1 0 t p7 t p3 en _ b k buc k en _ l d o 1 l d o 1 en _ l d o 2 l d o 2 supervisor a vi n 088 1 1-068 figure 67 . evaluation board schematic suggested layout 0 . 5 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 3 . 5 4 . 0 4 . 5 5 . 0 5 . 5 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 3 . 5 vi a s l eg en d m m m m 6 . 0 6 . 5 nc m o d e v i n 1 s w p g n d e n 1 4 . 0 4 . 5 5 . 0 5 . 5 6 . 0 c 6 - 1 0 f 6 . 3 v / x r 5 0 6 0 3 g p l g p l 1 . 5 v 3 . 3 v 7 . 0 t o p l a yer sec o nd l a yer pp l l1 ? 1h 0603 c5 ? 4.7 f 10v/xr5 0603 c 4 ? 1 f 6 . 3 v / x r 5 040 2 c 1 ? 1 f 10v / x r 5 0402 c 2 ? 1 f 10 v / x r 5 040 2 ppl = po w er pl an e (+4 v) g pl = g r o und pl an e 1 . 8 v a g n d ad p 5042 g p l g p l g p l g p l vout3 p i n 1 vin3 wdi2 vin2 vout2 wstat e n 2 n c w d i 1 w m o d vout1 m r nrsto e n c 3 ? 1 f 6 . 3 v / x r 5 0402 en3 r filt 30 ? 040 2 g p l g p l g p l g p l g p l p p l p p l p p l 8 1 1-069 figure 68 . layout
ADP5042 data sheet rev. a | page 28 of 32 bill of material s table 15. reference value part number vendor package c 1 , c 2 , c 3 , c 4 1 f, x5r, 6.3 v lmk105bj105mv - f taiyo yuden 0402 c5 4.7 f, x5r, 10 v lmk107bj475ma - t taiyo yuden 0603 c6 10 f, x5r, 6.3 v jmk107bj106ma - t taiyo yuden 0603 r filt 30 0201/0402 l1 1 h, 0.09 , 290 ma brc 1608t1r0m taiyo yuden 0603 1 h, 0.08 , 230 ma glfr1608t1r0m -lr tdk 0603 ic1 3- regulator micro pmu adp504 2 analog devices 20- lead l fcsp application diagram o n o f f f pw m pw m/ psm o n o f f r 1 r filt 30? r 2 po f f sw vo u t 1 pg n d mo d e c 6 10 f l 1 1 h vi n 1 en 3 en 1 vi n 2 vi n 3 en 2 a g n d c 2 1 f vo u t 2 vo u t 3 n c en2 w st a t w d i 2 w d i 1 n r st o c 4 1 f c 5 4 . 7 f v i n 1 = 2 . 3 v t o 5 . 5 v a vi n a vi n v i n 2 = 1 . 7 v t o 5 . 5 v c 1 1 f v i n 3 = 1 . 7 v t o 5 . 5 v c 3 1 f vo u t 1 a t 800m a vo u t 2 a t 300m a vo u t 3 a t 300m a en _ b k buc k en _ l d o 1 l d o 1 (d igi t a l ) en _ l d o 2 l d o 2 (ana l og ) su per vi so r a vi n o n o f f o n o f f 4 2 0 1 6 1 3 1 0 7 6 3 2 1 1 6 w mo d 1 7 1 9 1 2 5 1 5 1 4 1 7 9 1 1 8 w d og 2 w d og 1 r eset v d d v d d pu sh -bu tto n r eset mr main microcontroller 088 1 1-070 figure 69 . application di agram
data sheet ADP5042 rev. a | page 29 of 32 factory programmable options table 16 . reset voltage threshold options 1 selection t a = +25c t a = ?40c to +85c unit min typ max min max 111 (for vin = 5 v ? 6%) 4.630 4.700 v 110 (for vout = 3.3 v) 3.034 3.080 3.12 6 3.003 3.157 v 101 (for vout = 3.3 v) 2.886 2.930 2.974 2.857 3.000 v 100 (for vout = 2.8 v) 2.591 2.630 2.669 2.564 2.696 v 011 (for vout = 2.8 v) 2.463 2.500 2.538 2.438 2.563 v 010 (for vout = 2.5 v ? 6%) 2.350 2.385 v 001 (for vout = 2.2 v ? 6 %) 2.068 2.099 v 000 (for vout = 1.8 v ? 6%) 1.692 1.717 v table 17 . reset timeout options selection min typ max unit 0 24 30 36 ms 1 160 200 240 ms table 18 . watchdog 1 timer options selection min typ max unit 0 81.6 102 122.4 ms 1 1.12 1.6 1.92 sec table 19 . watchdog 2 timer options selection min typ max unit 000 6 7.5 9 sec 001 w atchdog 2 disabled 010 3.2 4 4.8 min 011 6.4 8 9.6 min 100 12.8 16 19.2 min 101 25.6 32 38.4 min 110 51.2 64 76.8 min 111 102.4 128 153.6 min table 20 . power - off timing options selection min typ max unit 0 140 200 280 ms 1 280 400 560 ms table 21 . reset sensing options selection monitor ed rail 00 vout1 pin 01 vout2 pin 10 vout3 pin 11 avin 1 pin 1 when monitoring avin , the reset threshold selected, by fuse option or by the external resistor divided, must be higher than the uvlo threshold (2.25 v or 3.6 v).
ADP5042 data sheet rev. a | page 30 of 32 outline dimensions 0.50 bsc 0.50 0.40 0.30 0.30 0.25 0.20 compliant to jedec standards mo-220-wggd. 061609-b bottom view top view exposed pad p i n 1 i n d i c a t o r 4.10 4.00 sq 3.90 seating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indicator 2.65 2.50 sq 2.35 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 1 20 6 10 11 15 16 5 figure 70. 20-lead, lead frame chip scale package [lfcsp_wq] 4 mm 4 mm body, very very thin quad (cp-20-10) dimensions shown in millimeters ordering guide model 1, 2 regulator settings supervisory settings temperature range package description package option ADP5042acpz-1-r7 vout1 = 1.8 v wd1 t out = 1.6 sec t j = ?40c to +125c 20-lead, lead frame scale package [lfcsp_wq] cp-20-10 vout2 = 1.5 v wd2 t out = 128 min vout3 = 3.3 v reset t out = 200 ms uvlo = 2.2 v poff = 200 ms sequencing: ldo1, ldo2, buck vth sensing = vout3, 2.93 v ADP5042acpz-2-r7 vout1 = 1.5 v wd1 t out = 1.6 sec t j = ?40c to +125c 20-lead, lead frame scale package [lfcsp_wq] cp-20-10 vout2 = 1.8 v wd2 t out = 128 min vout3 = 3.3 v reset t out = 200 ms uvlo = 2.2 v poff = 200 ms sequencing: ldo1, ldo2, buck vth sensing = vout3, 2.93 v ADP5042cp-1-evalz evaluation board ADP5042cp-2-evalz evaluation board 1 z = rohs compliant part. 2 monitoring ambient temperature does not guarantee that the junction temperature (t j ) is within the specified temperature limits.
data sheet ADP5042 rev. a | page 31 of 32 notes
ADP5042 data sheet rev. a | page 32 of 32 notes ?2010-2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d08811-0-11/11(a)

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